There is a continuing trend to increase the number and speed of circuits on integrated circuit (IC) chips. As a result of this drive toward ultra large scale integration, the size of various features decreases thereby increasing the number of devices on a chip. In order to take advantage of a large number of devices and form them into a large number of circuits, it is necessary to interconnect various zones, regions, connections and electrodes on the semiconductor substrate. For example, it is often necessary to connect selectively gate electrodes to source/drain diffusions, gate electrodes together and source/drain regions together. Local interconnects provide electrical connections in these instances.
A local interconnect providing an electrical connection between a source/drain region and gate electrode is desirable because it improves circuit density. Such a local interconnect is also desirable because it increases flexibility in circuit design. However, there are problems associated with forming such a local interconnect.
For instance, during the oxide etch process, it is desired to etch a portion of an oxide layer thereby exposing an etch stop layer, typically a nitride layer deposited over the entire device. But the etching rate of nitride at a poly gate corner is markedly faster than the etching rate of nitride at the flat area. Consequently, the oxide etch process may undesirably etch the nitride layer at the poly gate corner leading to the exposure of the oxide spacer. Once the oxide spacer is exposed, the oxide etch process quickly removes the oxide spacer and in some instances a portion of an underlying oxide isolation region. This phenomenon is termed trenching and is illustrated in FIG. 1. The trenching phenomenon is a problem because it causes device failure.
Referring to FIG. 1, there is a wafer substrate 10 with at least one device 12, such as field effect transistor. Shown is poly gate 14 on the substrate 10 and a titanium silicide layer 16 over the poly gate 14. Also shown are oxide spacers 18 adjacent the poly gate 14, nitride etch stop layer 20 and oxide layer 22, which is etched away by an oxide etching process. FIG. 1 shows the unintended etching of the nitride etch stop layer 20 which leads to the undesirable formation of a trench 24. The trench 24 is characteristic of the problematic trenching phenomenon. At the poly gate corner 26, the etching rate of nitride layer 20 is faster than the etching rate of nitride at the flat area 28.
In order to prevent etching of the nitride etch stop layer and the consequent trenching phenomenon, testing procedures have been developed to monitor the progress of etch oxide process. Current testing procedures include destructive testing that involves dissecting the IC or subjecting the IC to excessive conditions to induce failure. Dissection and maximum tolerance testing are beneficial because they offer critical information about the internal construction, durability and projected lifespan of the IC. Additionally, due to the geometrical constraints of the etched local interconnect structure, destructive tests are required to measure the nitride etch stop layer at the poly gate corner.
Present destructive tests include dissecting a IC and viewing it with a scanning electron microscope (SEM), scanning tunneling microscope (STM) or similar apparatus. Moreover, there are destructive tests for determining maximum thermal stress and voltage breakdown of a IC. The thermal stress test is destructive because it measures maximum thermal stress until the IC fails. The voltage breakdown test is destructive because it measures input voltage until the IC dielectric breaks down and the IC short circuits.
In traditional IC manufacturing, when a fabrication run is made, several thousand or more ICs are produced. From that fabrication run, many ICs are sampled out from the production and identified for destructive testing. The destructive test examples given above are typical of the tests performed. The rationale is that a statistical sample will demonstrate characteristics analogous to each of the ICs produced in the fabrication run. Destructive testing, however, can only provide information about the devices actually tested. Thus, devices in the same fabrication run are assumed to be analogous to the sampled IC.
A drawback to present testing techniques is that testing is mostly performed after the IC fabrication is complete. This may result in unnecessarily finishing an IC that exhibits trenching characteristics. Destructive testing is also expensive. Moreover, in light of the trend from 200 mm wafers towards the use of 300 mm wafers, destructive testing is even more expensive.
What is needed is a nondestructive method of inspecting ICs during fabrication processing. By inspecting the wafers during intermediate IC fabrication steps, useful information can be obtained about the evolving wafer, and in particular the local interconnect etch process. Further, if these techniques are nondestructive, substantially more wafers or even every wafer can be tested and those meeting test criteria can be sent on for further fabrication while those not meeting test criteria can be either discarded or sent back for remedial action. In addition, the local interconnect etch process for subsequent wafers can be adjusted to avoid the problems identified by the testing of earlier processed wafers. An in-line nondestructive test directly promotes higher IC yield and longer IC life.